The x86_64 version of IDMS Linux a PURE 64-bit build, allowing the user to benefit from all advantages this architecture has compared to i586. There are no 32-bit binaries included and all 64-bit binaries are optimized for 64-bit processors.

Features of IDMS Linux 64-Bit include:

• No memory segmentation in low and high memory

• Up to 128TiB virtual address space per process (instead of 2GiB)

This means that very large files can be operated on by mapping the entire file into the process' address space (which is sometimes faster than working with file read/write calls), rather than having to map regions of the file into and out of the address space.

• 64TiB physical memory support

32-bit systems can only map up to 3.4GiB, anything over this requires PAE. PAE requires 256MiB RAM mapping space.

• 64-bit CPUS have 16 general purpose registers, apposed to the 32-bit processor with only 8

In addition to increasing the size of the general-purpose registers, the number of named general-purpose registers is increased from eight (i.e. eax,ebx,ecx,edx,ebp,esp,esi,edi) in x86-32 to 16. It is therefore possible to keep more local variables in registers rather than on the stack, and to let registers hold frequently accessed constants; arguments for small and fast subroutines may also be passed in registers to a greater extent.

Additional XMM (SSE) registers: Similarly, the number of 128-bit XMM registers (used for Streaming SIMD instructions) is also increased from 8 to 16.

• Instruction pointer relative data access

Instructions can now reference data relative to the instruction pointer (RIP register). This makes position independent code more efficient.

• 64-bit integer capability

All general-purpose registers (GPRs) are expanded from 32 bits to 64 bits, and all arithmetic and logical operations, memory-to-register and register-to-memory operations, etc. can now operate directly on 64-bit integers. Pushes and pops on the stack are always in 8-byte strides, and pointers are 8 bytes wide.

• Optimized for SSE2 math (instead of 387 FPU)

SSE2 extends MMX instructions to operate on XMM registers, allowing the programmer to completely avoid the eight 64-bit MMX registers "aliased" on the original IA-32 floating point register stack. This permits mixing integer SIMD and scalar floating point operations without the mode switching required between MMX and x87 floating point operations. However, this is over-shadowed by the value of being able to perform MMX operations on the wider SSE registers.

Other SSE2 extensions include a set of cache-control instructions intended primarily to minimize cache pollution when processing indefinite streams of information, and a sophisticated complement of numeric format conversion instructions.

SSE2 instructions can also operate on twice as much data as an MMX instruction.

• Compiled optimization with a common base for AMD64/EM64T

• Memory pages are not executable by default

The "NX" bit (bit 63 of the page table entry) allows the operating system to specify which pages of virtual address space can contain executable code and which cannot. An attempt to execute code from a page tagged "no execute" will result in a memory access violation, similar to an attempt to write to a read-only page. This should make it more difficult for malicious code to take control of the system via "buffer overrun" or "unchecked buffer" attacks.

Native execution of legacy 32bit binaries is supported by the kernel, primarily for virtualized ix86 applications.

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